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CY28341-2
Universal Clock Chip for VIATMP4M/KT/KM400 DDR Systems
Features
* * * * * Supports VIA P4M/KM/KT/266/333/400 chipsets Supports Pentium(R) 4, AthlonTM processors Supports two DDR DIMMS Supports three SDRAM DIMMS at 100 MHz Provides: -- two different programmable CPU clock pairs -- six differential SDRAM DDR pairs -- three low-skew/-jitter AGP clocks -- seven low-skew/-jitter PCI clocks -- one 48M output for USB -- one programmable 24M or 48M for SIO * Dial-a-Frequency and Dial-a-dB features * Spread Spectrum for best electromagnetic interference (EMI) reduction * Watchdog feature for system recovery * SMBus-compatible for programmability * 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 66.80 100.00 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.00 180.00 166.6 90.00 100.00 200.00 133.33 AGP 66.80 66.80 60.00 66.67 72.00 70.00 64.00 70.00 77.00 73.33 60.00 66.6 60.00 66.67 66.67 66.67 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 33.3 30.00 33.33 33.33 33.33
Block Diagram
XIN XOUT XTAL REF0 VDDR REF(0:1) VDDI CPUCS_T/C
FS0
Pin Configuration[1]
*FS0/REF0 VSSR XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 AGP2 VSSAGP **FS1/PCI_F **SELSDR_DDR/PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT0/SDRAM0 DDRC0/SDRAM1 DDRT1/SDRAM2 DDRC1/SDRAM3 VDDD VSSD DDRT2/SDRAM4 DDRC2/SDRAM5 DDRT3/SDRAM6 DDRC3/SDRAM7 VDDD VSSD DDRT4/SDRAM8 DDRC4/SDRAM9 DDRT5/SDRAM10 DDRC5/SDRAM11
SELP4_K7#
VDDC CPU(0:1)/CPU0D_T/C VDDPCI
FS2
PLL1 FS3 FS1
PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M
/2
CY28341-2
PD#
SDATA SCLK
SMBus
PLL2 WDEN
24_48M
WD SELSDR_DDR Buf_IN S2D CONVERT
SRESET# VDDD FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) DDRC(0:5)/SDRAM(1,3,5,7,9,11)
56 pin SSOP
Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation Document #: 38-07471 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 22, 2003
CY28341-2
Pin Description [2]
Pin Number 3 4 1 XIN XOUT FS0/REF0 VDDR 56 VTTPWRGD# VDDR I VDD Pin Name PWR I/O I O Pin Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN.
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS0 state is PU latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up, VTT_PWRGD# is an input. When this input transitions to a logic low, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first high to low transition on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10K resistor. If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REF1 and is a buffered copy of the signal applied at XIN. These pins are programmable through strapping pin11, SELSDR_DDR#. If SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "True" copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V These pins are programmable through strapping pin11, SELSDR_DDR#. If SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "Complementary" copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for SDRAM(1,3,5,7,9,11) single ended clock outputs, copies of (and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
REF1 VDDR 44,42,38, 36,32,30 DDRT (0:5)/SDRAM (0,2,4,6,8,10) O
VDDD
O
43,41,37 35,31,29
DDRC (0:5)/SDRAM (1,3,5,7,9,11)
VDDD
O
7
SELP4_K7 / AGP1
Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input. I/O When the power supply voltage crosses the input threshold voltage, VDDAGP PU SELP4_K7 state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode. VDDPCI Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. I/O When the power supply voltage crosses the input threshold voltage, MULTSEL PU state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF O 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 1 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 1 2.5V CPU Clock Outputs for Chipset. See Table 1. PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1
12
MULTSEL/PCI2
53
CPUT/CPUOD_T VDDC
52
CPUC/CPUOD_C VDDC O O O
48,49 10
CPUCS_T/C FS1/PCI_F
VDDI VDDPCI VDDPCI
14,15,17,18 PCI (3:6)
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS1 state is PD latched and this pin becomes PCI_F clock output. Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS3 state is PD latched and this pin becomes 48M, a USB clock output.
20
FS3/48M VDD48M
Note: 2. PU = internal pull-up. PD = internal pull-down. Typically =250 kW (range 200 k to 500 k).
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CY28341-2
Pin Description [2] (continued)
Pin Number 11 Pin Name SELSDR_DDR#/ PCI1 PWR VDDPCI I/O Pin Description Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the I/O input. When the power supply voltage crosses the input threshold voltage, PD SELSDR_DDR state is latched and this pin becomes PCI clock output. SelSDR_DDR#.= 0, DDR Mode. SelSDR_DDR#.= 1, SDR Mode. Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS2 state is PD latched and this pin becomes 24_48M, a SIO programmable clock output. O O I AGP Clock Output. Is synchronous to CPU clocks. See Table 1 AGP Clock Output. Is synchronous to CPU clocks. See Table 1 Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference.
21
FS2/24_48M VDD48M
6 8 25 28
AGP0 AGP2 IREF SDATA
VDDAGP VDDAGP
Serial Data Input. Conforms to the Phillips I2C specification of a Slave I/O Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the Philips I2C specification. Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default), this pin becomes a SRESET# open drain output. See system reset description. I/O If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When PU PD# is asserted low, the device enters power down mode. See power management function. If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential buffers. If SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer. If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the SDRAM(0:11) signals 3.3V power supply for AGP clocks 3.3V power supply for CPUT/C clocks 3.3V power supply for PCI clocks 3.3V power supply for REF clock 2.5V power supply for CPUCS_T/C clocks 3.3V power supply for 48M 3.3V Common power supply If SelSDR_DDR#.= 0, 2.5V power supply for DDR clocksIf SelSDR_DDR#.= 1, 3.3V power supply for SDR clocks. Ground for AGP clocks Ground for PCI clocks Ground for CPUT/C clocks Ground for DDR clocks Ground for 48M clock Ground for ICPUCS_T/C clocks Ground for REF Common Ground
27 26
SCLK PD#/SRESET#
45 46
BUF_IN FBOUT
5 51 16 55 50 22 23 34,40 9 13 54 33,39 19 47 2 24
VDDAGP VDDC VDDPCI VDDR VDDI VDD_48M VDD VDDD VSSAGP VSSPCI VSSC VSSD VSS_48M VSSI VSSR VSS
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CY28341-2
Power Management Functions
All clocks can be individually enabled or stopped via the two-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.5 mS. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol.The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation. 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be `0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
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CY28341-2
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `1xxxxxxx' stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Byte Count - 8 bits Acknowledge from slave stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `1xxxxxxx' stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge stop Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Serial Control Registers
Byte 0: Frequency Select Register Bit 7 6 5 4 3 @Pup 0 H/W Setting H/W Setting H/W Setting 0 21 10 1 Pin# Name Reserved FS2 FS1 FS0 Reserved For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 If this bit is programmed to "1", it enables WRITE to bits (6:4,1) for selecting the frequency via software (SMBus) If this bit is programmed to a "0" it enable only READ of bits (6:4,1), which reflect the hardware setting of FS(0:3). 11 20 7 SELSDR_DDR Only for reading the hardware setting of the SDRAM interface mode, status of SELSDR_DDR# strapping. FS3 SELP4_K7 For Selecting frequencies in Frequency Selection Table on page 1 Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Description
2 1 0
H/W Setting H/W Setting H/W Setting
Byte 1: CPU Clocks Register Bit 7 6 5 4 3 2 1 @Pup 0 1 1 1 1 1 1 Pin# MODE SSCG SST1 SST0 48,49 CPUCS_T, CPUCS_C 53,52 CPUT/CPUOD_T CPUC/CPUOD_C 53,52 CPUT/C Name Description 0 = Down Spread. 1 = Center Spread. See Table 9 on page 9 1 = Enable (default). 0 = Disable Select spread bandwidth. See Table 9 on page 9 Select spread bandwidth. See Table 9 on page 9 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disable. In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW, CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when PD# asserted LOW, CPUT and CPUC stop in High-Z. Only for reading the hardware setting of the Pin11 MULT0 value. Page 5 of 19
0
1
11
MULT0
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CY28341-2
Byte 2: PCI Clock Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 10 18 17 15 14 12 11 Pin# Name PCI_DRV PCI_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Description PCI clock output drive strength 0 = Low strength, 1 = High strength 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 3: AGP/Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 0 0 1 1 1 Pin# 21 20 21 6,7,8 6,7,8 8 7 6 Name 24_48M 48MHz 24_48M DASAG1 DASAG0 AGP2 AGP1 AGP0 Description 0 = pin21 output is 24 MHz. Writing a '1' into this register asynchronously changes the frequency at pin21 to 48 MHz. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low Programming these bits allow shifting skew of the AGP(0:2) signals relative to their default value. See Table 5. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low
Table 5. Dial-a-Skew AGP(0:2) DASAG (1:0) 00 01 10 11 Byte 4: Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 1 1 1 1 Pin# 20 21 6,7,8 6,7,8 1 56 1 56 48M 24_48M DARAG1 DARAG0 REF0 REF1 REF0 REF1 Name Description 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength (K7 Mode only) AGP(0:2) Skew Shift Default -280 ps +280 ps +480 ps
Table 6. Dial-A-Ratio AGP(0:2) DARAG (1:0) 00 01 10 11 CU/AGP Ratio Frequency Selection Default 2/1 2.5/1 3/1
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CY28341-2
Byte 5: SDR/DDR Clock Register Bit @Pup Pin# 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 45 46 Name BUF_IN threshold voltage FBOUT Description DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN threshold setting. 0 = 1.35V, 1 = 1.25V 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
29,30 DDRT/C5/SDRAM(10,1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1) 31,32 DDRT/C4/SDRAM(8,9) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 35,36 DDRT/C3/SDRAM(6,7) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 37,38 DDRT/C2/SDRAM(4,5) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 41,42 DDRT/C1/SDRAM(2,3) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 43,44 DDRT/C0/SDRAM(0,1) 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 6: Watchdog Register Bit @Pup Pin# 7 6 0 0 26 Name SRESET# Frequency Revert Description 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only.0 = selects frequency of existing H/W setting1 = selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). For IMI Test - WD-Test, ALWAYS program to '0' This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7
5 4 3 2 1 0
0 0 0 0 0 0
WDTEST WD Alarm WD3 WD2 WD1 WD0
Table 7. Watchdog Time Stamp WD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
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CY28341-2
Byte 7: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved N6, MSB N5 N4 N3 N2 N3 N0, LSB Description Reserved for device function test. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock.
Byte 8: Silicon Signature Register (all bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress's Vendor ID bit [3]. Cypress's Vendor ID bit [2]. Cypress's Vendor ID bit [1]. Cypress's Vendor ID bit [0]. Description
Byte9: Dial-A-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is load from DAF (SMBus) registers. Pin# Name Reserved These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via Byte7 and Byte9. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature. Table 8. FS(4:0) XXXXX P 96016000
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CY28341-2
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7. Table 9. Spread Spectrum Table Mode 0 0 0 0 1 1 1 1 SST1 0 0 1 1 0 0 1 1 SST0 0 1 0 1 0 1 0 1 % Spread +0.14, -1.23 +0, -1.00 +0, -0.60 +0, -0.52 +0.72, -0.71 +0.47, -0.49 +0.34, -0.33 +0.30, -0.28
Swing Select Functions Through Hardware
MULTSEL 0 1 Board Target Trace/Term Z 50 Ohm 50 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00mA Rr = 475 1%, IREF = 2.32mA Output Current IOH = 4* Iref IOH = 6* Iref VOH@Z 1.0V@50 0.7V@50
System Self Recovery Clock Management
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. When the system sends an SMBus command requesting a frequency change through Byte 4 or through bytes 13 and 14, it must have previously sent a command to byte 12, for selecting which time out stamp the Watchdog must perform, otherwise the System Self Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in Byte 12, bits (3:0) (reprogram to 0000),
before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. If the Watchdog times out the first time before the new SMBus reprograms Byte 12, bits (3:0) to (0000), then this device will send a low system reset pulse, on SRESET# (see byte12, bit7), and changes WD alarm (Byte12, Bit4) status to "1" then restarts the Watchdog timer again. If the Watchdog times out a second time, then this device will send another low pulse on SRESET#, will relatch original hardware strapping frequency (or second to last software selected frequency, see byte12, bit6) selection, set WD alarm bit (Byte12, bit4) to `1,' then start WD timer again. The above-described sequence will keep repeating until the BIOS clears the SMBus byte12 bits (3:0). Once the BIOS sets Byte 12 bits (3:0) = 0000, then the Watchdog timer is turned off and the WD alarm bit (Byte 12, bit4) is reset to `0.'
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CY28341-2
S y s t e m r u n n in g w it h o rig in a lly s e le c te d fre q u e n c y v ia h a r d w a r e s tr a p p in g .
No F r e q u e n c y w ill c h a n g e b u t S y s t e m S e lf R e c o v e r y n o t a p p lic a b le ( n o t im e s t a m p s e le c t e d a n d b y t e 1 2 , b it ( 3 : 0 ) is s t ill = "0 0 0 0 " R e c e iv e F r e q u e n c y C h a n g e R e q u e s t v ia S M B u s B y t e 4 o r V ia D ia la -fre q u e n c y ? Yes
No Is S M B u s B y te 9 , tim e o u t s t a m p e n a b le d - ( b y t e 1 2 , b it (3 :0 ) 0 0 0 0 )?
C h a n g e to a n e w fre q u e n c y
1 ) S e n d a n o th e r 3 m S lo w p u ls e o n S 2 ) R e la tc h o r ig in a l h a r d w a r e s tr a p p in f o r r e t u r n t o o r ig in a l f r e q u e n c y s e t t in g 3 ) S e t W D A la r m b it ( b y t e 1 2 , B it 4 ) t o 4 ) S ta r t W D tim e r Y es
RESET g s e le c t io n s. "1 "
Yes S t a r t in t e r n a l w a t c h d o g t im e r .
W a tc h D o g tim e o u t?
1) Send S R ES ET p u ls e 2 ) S e t W D b it ( b y t e 1 2 , b it 4 ) t o '1 ' 3 ) S ta r t W D tim e r
Yes
W a t c h D o g t im e o u t ?
No
No S M B u s b y te 1 2 tim e o u t s ta m p d is a b le d ? S M B u s b y te 9 tim e o u t s ta m p d is a b le d , B y te 1 2 , b it(3 :0 ) = (0 0 0 0 ) ? Y es Yes T u r n o ff w a tc h d o g tim e r. K e e p n e w f r e q u e n c y s e t t in g . S e t W D b i t ( b y t e 1 2 , b i t 4 ) t o ''0 ' No
No
a la rm
Figure 1. Watchdog Recovery Clock
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode): When PD# is sampled low by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. Note that Figure 1 shows CPU =
PW RDW N# CPUT 133M Hz CPUT# 133M Hz PCI 33M Hz AG P 66M Hz USB 48M Hz R E F 1 4 .3 1 8 M H z D DRT 133M Hz DDR C 133M Hz SD RAM 133M Hz
133 MHz. This diagram and description are applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Figure 2. Power-down Assertion Timing Waveform (in P4 mode)
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CY28341-2
Power-down Deassertion (P4 Mode) The power-up latency needs to less than 3 mS.
< 1 .5 m s e c PW RDW N# CPU 133MHz C PU# 133MHz PCI 33MHz AGP 66MHz USB 48MHz R E F 1 4 .3 1 8 M H z D DRT 133MHz DD RC 133MHz SDR AM 133MHz
Figure 3. Power-down Deassertion Timing Waveform (in P4 mode)
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode): When the PD# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode and all power supplies may then be removed. When PD# is sampled low by two consecutive rising edges of CPU clock, then all affected
PW RDW N# C P U O D _T 133M H z C P U C S _T 133M H z C P U O D _C 133M H z C P U C S _C 133M H z P C I 33M H z A G P 66M H z U S B 48M H z R E F 14.318M H z D D R T 133M H z D D R C 133M H z S D R A M 133M H z
clocks are stopped in a low state as soon as possible. When in power down (and before power is removed), all outputs are synchronously stopped in a low state (see Figure 3 below), all PLL's are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled.
Figure 4. Power-down Assertion Timing Waveform (in K7 mode)
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CY28341-2
Power-down Deassertion (K7 Mode): When deasserted PD# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch-free operation, no partial clock pulses.
< 1 .5 m se c PW RDW N# CPU 133MHz CPU# 133MHz PCI 33MHz AGP 66MHz USB 48MHz R E F 1 4 .3 1 8 M H z DDRT 133MHz DDRC 133MHz SDRAM 133MHz
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)
VID (0:3), SEL (0,1) VTT_PW RGD# PW RGD
VDD Clock Gen Clock State State 0
0.2-0.3m S Delay State 1
W ait for VTT_GD#
Sam ple Sels State 2 State 3 (Note A)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)[3]
Note: 3. This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored.
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CY28341-2
WR TP
S1
=L
ow
GD
#
S2
D e la y 0 .2 5 m S
S a m p le In p u ts F S ( 3 :0 )
W a it fo r 1 .1 4 6 m s
VT
E n a b le O u tp u te s
V D D A = 2 .0 V
S0
S3
P o w e r O ff
V D D 3 .3 = O f f
N o rm a l O p e r a tio n
Figure 7. Clock Generator Power-up/Run State Diagram (with P4 processor SELP4_K7#=1)
Connection Circuit DDRT/C Signals
For open-drain CPU output signals (with K7 processor SELP4_K7#=0)
3.3V 150 Ohm CPUOD_T 47 Ohm 52 Ohm 5" 680 pF 3.3V 301 Ohm 47 Ohm CPUOD_C 150 Ohm 52 Ohm 5" 680 pF 60.4 Ohm 500 Ohm VDDCPU(1.5V) 20 pF VDDCPU(1.5V) 52 Ohm 1" 500 Ohm 500 Ohm VDDCPU(1.5V) 60.4 Ohm 52 Ohm 1" 20 pF VDDCPU(1.5V) 500 Ohm
Measurem ent Point
Measurem ent Point
Figure 8. K7 Load Termination
6"
6"
Figure 9. CS Load Termination Table 10. Signal Loading Table Clock Name REF (0:1), 48MHz (USB), 24_48MHz AGP(0:2), SDRAM (0:11) PCI_F(0:5) DDRT/C (0:5), FBOUT CPUT/C CPUOD_T/C CPUCS_T/C Document #: 38-07471 Rev. *B Max Load (in pF) 20 30 30 See Figure 10 See Figure 8 See Figure 9 Page 13 of 19 For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1) The following diagram shows lumped test load configurations for the differential Host Clock outputs.
CY28341-2
T PCB CPUT RtA1 MULTSEL CPUT# RtA2 T PCB RLA2 R LB2 RtB2 C LB RLA1 R LB1 RD CLK Measurement Point RtB1 C LA CLK Measurement Point
R ref
Figure 10. P4 Load Termination Table 11. Lumped Test Load Configuration Component RtA1, RtA2 RLA1, RLA2 TPCB RLB1, RLB2 RD RtB1, RtB2 CLA, CLB Rref 33 49.9 3" 50 Z 0 2 pF 475 w/mult0 = 1 0.7V Amplitude Value 0 3" 50 Z 63 470 33 2 pF 221 w/mult0 = 0 1.0V Amplitude Value
Group Timing Relationships and Tolerances[4]
Offset (ps) tCSAGP tAP CPUCS to AGP AGP to PCI 750 1,250 Tolerance (ps) 500 500 Conditions CPUCS Leads AGP Leads
0ns
10ns
20ns
30ns
CPU CLOCK 66.6MHz CPU CLOCK 100MHz CPU CLOCK 133.3MHz tCSAGP AGP CLOCK 66.6MHz tAP PCI CLOCK 33.3MHz
Note: 4. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same length transmission line should be added to the other signal of the pair (e.g., AGP).
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CY28341-2
Maximum Ratings[5]
Input Voltage Relative to VSS:.............................. VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature: .................................... 0C to +70C Maximum ESD .............................................................2000V Maximum Power Supply: ................................................5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field. However, precautions should be take to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD.
DC
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Parameters (VDD=VDDPCI=VDDAGP=VDDR=VDD48M=VDDC= 3.3v5%, VDDI = VDD=2.55%, TA=0C TO +70C) Description Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage for SRESET# Pull-down current for SRESET# Three-state leakage Current Dynamic Supply Current Dynamic Supply Current Power-down Supply current Internal Pull-up Device Current Internal Pull-down Device Current Input pin capacitance Output pin capacitance Pin Inductance Crystal pin capacitance Conditions Applicable to PD#, F S(0:4) Applicable to SDATA and SCLK IOL VOL = 0.4V CPU frequency set at 133.3 MHz, Note 6 CPU frequency set at 133.3 MHz, Note 6 PD# = 0 Input @ VSS Input @ VDD 2.2 0.4 24 Min. 2.0 1.0 Typ. Max. 0.8 Unit Vdc Vdc Vdc Vdc V mA A mA mA A A A pF pF pF pF
Parameter VIL1 VIH1 VIL2 VIH2 VOL IOL IOZ IDD3.3V IDD2.5V IPD IPUP IPDWN CIN COUT LPIN CXTAL
35 150 175 95 10 190 195 600 -25 10 5 6 7 45
Measured from the Xin or Xout to VSS
27
36
AC Parameters
Parameter Description XTAL TDC Xin Duty Cycle TPERIOD Xin Period VHIGH Xin High Voltage VLOW Xin Low Voltage TR/TF Xin Rise and Fall Times TCCJ Xin Cycle to Cycle Jitter TXS Crystal Start-up Time P4 Mode CPU at 0.7V TDC CPUT/C Duty Cycle TPERIOD CPUT/C Period 100 MHz Min. Max. 45 69.84 .7VDD 0 55 71.00 VDD .3VDD 10.0 500 30 55 10.2 133 MHz Min. Max 45 69.84 .7VDD 0 55 71.0 VDD .3VDD 10 500 30 55 7.65 200 MHz Min. Max. Unit 45 69.84 .7VDD 0 55 71.0 VDD .3VDD 10 500 30 55 5.1 % ns V V ns ps ms Notes 7,14 7,14 12 15 13 8,11 10,12
45 9.85
45 7.35
45 4.85
% 7,8,9,15, 16 ns 7,8,9,15, 16
Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. All outputs loaded as per maximum capacitive load table. 7. This parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 MHz. 8. All outputs loaded as per loading specified in theTable 11. 9. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals. 10. Probes are placed on the pins, and measurements are acquired at 0.4V. 11. When Xin is driven from and external clock source (3.3V parameters apply). 12. When crystal meets minimum 40-ohm device series resistance specification. 13. Measured between 0.2VDD and.7VDD. 14. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 15. Measured at VX, or where subtraction of CLK-CLK# crosses 0V. 16. See Figure 10 for 0.7V loading specification.
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CY28341-2
AC Parameters (continued)
100 MHz 133 MHz Description Min. Max. Min. Max CPUT/C Rise and Fall Times 175 700 175 700 Rise/Fall Matching 20% 20% Rise/Fall Time Variation 125 125 TR/TF TSKEW CPUCS_T/C to CPUT/C Clock Skew 0 200 0 150 TCCJ CPUT/C Cycle to Cycle Jitter -150 +150 -150 +150 VCROSS Crossing Point Voltage at 0.7V Swing 280 430 280 430 P4 Mode CPU at 1.0V TDC CPUT/C Duty Cycle 45 55 45 55 TPERIOD CPUT/C Period 9.85 10.2 7.35 7.65 Differential CPUT/C Rise and Fall times 175 467 175 467 TR/TF TSKEW CPUCS_T/C to CPUT/C Clock Skew 0 200 0 150 TCCJ CPUT/C Cycle to Cycle Jitter -150 +150 -150 +150 VCROSS Crossing Point Voltage at 1V Swing 510 760 510 760 SE-DeltaSlew Absolute Single-ended Rise/Fall 325 325 Waveform Symmetry K7 Mode TDC CPUOD_T/C Duty Cycle 45 55 45 55 TPERIOD CPUOD_T/C Period 9.98 10.5 7.5 8.0 TLOW CPUOD_T/C Low Time 2.8 1.67 TF CPUOD_T/C Fall Time 0.4 1.6 0.4 1.6 TSKEW CPUCS_T/C to CPUT/C Clock Skew 0 200 0 150 TCCJ CPUOD_T/C Cycle-to-Cycle Jitter -150 +150 -150 +150 VD Differential Voltage AC .4 Vp+.6V .4 Vp+.6V VX Differential Crossover Voltage 500 1100 500 1100 CHIPSET CLOCK TDC CPUCS_T/C Duty Cycle 45 55 45 55 TPERIOD CPUCS_T/C Period 10.0 10.5 15 15.5 TR / TF CPUCS_T/C Rise and Fall Times 0.4 1.6 0.4 1.6 VD Differential Voltage AC .4 Vp+.6V .4 Vp+.6V VX Differential Crossover Voltage 0.5*VD 0.5*VDDI 0.5*VD 0.5*VD +0.2 DI-0.2 DI-0.2 DI+0.2 AGP TDC AGP(0:2) Duty Cycle 45 55 45 55 TPERIOD AGP(0:2) Period 15 16 15 16 THIGH AGP(0:2) High Time 5.25 5.25 TLOW AGP(0:2) Low Time 5.05 5.05 TR / TF AGP(0:2) Rise and Fall Times 0.4 1.6 0.4 1.6 Parameter TR/TF 200 MHz Min. Max. Unit Notes 175 700 ps 24 20% 24,26 125 ps 8,24,16 0 200 ps 8,18,15,16 -200 +200 ps 8,18,15,16 280 430 mV 16 45 4.85 175 0 -200 510 55 5.1 467 200 +200 760 325 % 8,9,15 nS 8,9,15 ps 7,14,27 0 ps mV ps 8,14,11 8,14,11 27 26
45 55 % 5 5.5 ns 2.8 ns 0.4 1.6 ns 0 200 0 -200 +200 ps .4 Vp+.6V V 500 1100 mV
8,9 8,9 8,9 8,13 8,14,11 8,9 23 23
45 55 % 7,8,9 10.0 10.5 ns 7,8,9 0.4 1.6 ns 7,8,13 .4 Vp+.6V V 24 0.5*VD 0.5*VD V 11 DI-0.2 DI+0.2 45 15 5.25 5.05 0.4 55 16 % ns ns ns ns 7,8,9 7,8,9 8,21 8,10 8,13
1.6
Notes: 17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between 20% and 80% for differential signals. 18. This measurement is applicable with Spread ON or spread OFF. 19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals). 20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs. 21. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same. 22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary DDRC (and CPUCS_C) one. 23. Measured at VX between the rising edge and the following falling edge of the signal. 24. Measured from VOL = 0.175V to VOH = 0.525V. 25. Measurement taken from differential waveform, from -0.35V to +0.35V. 26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as "the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time". This parameter is designed for waveform symmetry. 27. Measured in absolute voltage, i.e., single-ended measurement.
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CY28341-2
AC Parameters (continued)
Parameter TSKEW TCCJ PCI TDC TPERIOD THIGH TLOW TR / TF TSKEW TCCJ 48 MHz TDC TPERIOD TR / TF TCCJ 24 MHz TDC TPERIOD TR / TF TCCJ REF TDC TPERIOD TR / TF TCCJ DDR VX VD TDC TPERIOD TR / TF TSKEW TCCJ THPJ TDELAY TSKEW TSTABLE Description Any AGP to Any AGP Clock Skew AGP(0:2) Cycle-to-Cycle Jitter PCI(_F,1:6) Duty Cycle PCI(_F,1:6) Period PCI(_F,1:6) High Time PCI(_F,1:6) Low Time PCI(_F,1:6) Rise and Fall Times Any PCI to Any PCI Clock Skew PCI(_F,1:6) Cycle-to-Cycle Jitter 48-MHz Duty Cycle 48-MHz Period 48-MHz Rise and Fall Times 48-MHz Cycle-to-Cycle Jitter 24-MHz Duty Cycle 24-MHz Period 24-MHz Rise and Fall Times 24-MHz Cycle-to-Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle-to-Cycle Jitter Crossing Point Voltage of DDRT/C Differential Voltage Swing DDRT/C(0:5) Duty Cycle DDRT/C(0:5) Period DDRT/C(0:5) Rise/Fall Slew Rate DDRT/C to any DDRT/C Clock Skew DDRT/C(0:5) Cycle-to-Cycle Jitter DDRT/C(0:5) Half-period Jitter BUF_IN to Any DDRT/C Delay FBOUT to Any DDRT/C Skew All-Clock Stabilization from Power-up 100 MHz Min. Max. 250 500 45 30.0 12.0 12.0 0.5 55 133 MHz Min. Max 250 500 45 30.0 12.0 12.0 0.5 55 200 MHz Min. Max. Unit Notes 250 ps 8,14 500 ps 8,9,14 45 30.0 12.0 12.0 0.5 55 % ns ns ns ns ps ps 7,8,9 7,8,9 8,21 8,10 8,13 8,14 8,9,14
2.5 500 500
2.5 500 500
2.5 500 500
45 55 45 55 45 55 % 7,8,9 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,8,9 1.0 4.0 1.0 4.0 1.0 4.0 ns 8,13 500 500 500 ps 8,9,14 45 41.660 1.0 55 41.667 4.0 500 55 71.0 4.0 1000 45 55 45 55 % 7,8,9 41.660 41.667 41.660 41.667 ns 7,8,9 1.0 4.0 1.0 4.0 ns 8,13 500 500 ps 8,9,14 45 69.841 3 1.0 55 71.0 4.0 1000 45 69.841 3 1.0 55 71.0 4.0 1000 % 7,8,9 ns 7,8,9 ns 8,13 ps 8,9,14
45 69.841 3 1.0
0.5*VD DD-0.2 0.7 45 9.85 1
1
0.5*VDDD 0.5*VD 0.5*VD 0.5*VD 0.5*VD V 15 +0.2 DD-0.2 DD+0.2 DD-0.2 DD+0.2 VDDD + 0.7 VDDD 0.7 VDDD V 23 0.6 + 0.6 + 0.6 55 45 55 45 55 % 11 10.2 14.85 15.3 9.85 10.2 ns 11 3 1 3 1 3 V/n 13 s 100 100 100 ps 8,14,11 75 75 75 ps 8,14,11 100 100 100 ps 8,14,11 4 1 4 1 4 ns 8,9 100 100 100 ps 8,9 3 3 3 ms 22
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CY28341-2
Ordering Information
Part Number CY28341OC-2 CY28341OC-2T CY28341ZC-2 CY28341ZC-2T Package Type 56-pin Shrunk Small Outline package (SSOP) 56-pin Shrunk Small Outline package (SSOP)-Tape and Reel 56-pin Thin Shrunk Small Outline package(TSSOP) 56-pin Thin Shrunk Small Outline package(TSSOP)-Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Package Drawing and Dimensions
56-pin Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
51-85060-*B
56-Lead Shrunk Small Outline Package O56
51-85062-*C
Purchase of components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. VIA is a trademark of VIA Technologies, Inc. Pentium 4 is a registered trademark of Intel Corporation. Athlon is a trademark of AMD Corporation, Inc. Dial-a-Frequency is a registered trademark, and Dial-a-Skew, Dial-a-dB, and Dial-a-Ratio are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07471 Rev. *B Page 18 of 19
I2C
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY28341-2
Document History Page
Document Title: CY28341-2 Universal Clock Chip for VIATMP4M/KT/KM400 DDR Systems Document Number: 38-07471 REV. ** *A *B ECN NO. 118589 122938 124914 Issue Date 09/18/02 12/19/02 04/23/03 Orig. of Change RGL RBI RGL New Data Sheet Add power up requirements to maximum ratings information Fixed pin 1 and pin 2 in Pin Description table Added KT400 feature to Features section Corrected Figure 8 (K7 Load Termination) diagram Simplified title Fixed Spread Spectrum table Description of Change
*C
127161
06/10/03
RGL
Document #: 38-07471 Rev. *B
Page 19 of 19

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